Integrated circuits have continued to shrink in size and increase in complexity with each new generation of devices. As a result, integrated circuits increasingly require very close spacing of interconnect lines and many now require multiple levels of metalization, as many as five, to interconnect the various circuits on the device. Since closer spacing increases capacitance between adjacent lines, as the device geometries shrink and densities increase capacitance and cross talk between adjacent lines becomes more of a problem. Therefore, it becomes increasingly more desirable to use lower dielectric materials to offset this trend and thereby lower capacitance between closely spaced interconnects.
Interconnect capacitance has two components: the line-to-substrate, or line-to-ground capacitance and line-line capacitance. For ultra large scale integration at 0.25 micron design rules and beyond, performance is dominated by interconnect RC delay, with line-to-line capacitance being the dominant contributor to total capacitance. For example, theoretical modeling has shown that when the width/spacing is scaled down below 0.3 micron, the interlayer capacitance is so small that total capacitance is dictated by the line-to-line capacitance, which constitutes more than 90% of the total interconnect capacitance. Therefore, a reduction of the line-line capacitance alone will provide a dramatic reduction in total capacitance.
The intermetal dielectric (IMD) of the prior art is typically SiO.sub.2 which has a dielectric constant of about 4.0. It would be desirable to replace this material with a material having a lower dielectric constant. As used herein, low dielectric constant or low-k means a material having a dielectric constant of lower than 4 and preferably lower than 3 and most preferably about 2 or lower. Unfortunately, materials having a lower dielectric constant have characteristics that make them difficult to integrate into existing integrated circuit structures and processes. Many polymeric materials such as polysilsequioxane, parylene, polyimide, benzocyclobutene and amorphous Teflon have lower dielectric constants (lower permitivities). Compared to SiO.sub.2, these low-k materials may have low mechanical strength, poor dimensional stability, poor temperature stability, high moisture absorption and permeation, poor adhesion, large thermal expansion coefficient and/or an unstable stress level. Because of these attributes, the use of polymer or other low dielectric materials as a stand alone replacement for SiO.sub.2 in integrated circuit processes or structures is very difficult if not impossible.
An earlier application, by Havemann, SN 08/250,142 assigned to Texas Instruments Inc. and incorporated herein by reference, disclosed a two-step metal etch process for selectively filling the gaps of narrowly spaced interconnects to reduce capacitance in VLSI circuits while using a structurally sturdy interlevel dielectric in non-critical areas.
Another application by applicant herein, SN 08/202,057, assigned to Texas Instruments Inc. and incorporated herein by reference, disclosed a method for filling narrow gaps with low dielectric constant materials.